Digital communication of information from a source to a receiver may be done source synchronously. Source synchronous communication involves a clock signal from the source (“source clock signal” or “forwarded clock signal”) being sent in parallel with other information from the source. Such other information may include data or control information, where control information includes address information. Hereinafter, such information is referred to as data, which includes one or more of data and control information.
There are different types of source synchronous communication, which may depend on the application. For example, in source synchronous communication between locally co-located integrated circuits, frequency of the source clock signal from a source integrated circuit may be known a priori by a receiving integrated circuit. An example of this type of source synchronous interface may be found in communication with synchronous memory, where a forwarded clock signal is sent in parallel with a data signal.
However, for example, in source synchronous communication in computer networks or telecommunications interfaces, such as between a transmitting device and a receiving device, frequency of a source clock signal may not be known by the receiving device. Furthermore, due to differences in signal propagation delays, there may be skew between information communicated in parallel with the source clock signal. For example, data on one channel may be askew from data on another channel.
For memory interfacing, and for some network interfacing, frequency of the forwarded clock signal and the frequency of the receiver integrated circuit interface are the same, though with the possibility of phase mismatch. In these same frequency applications, there were several conventional circuits used. One conventional circuit uses a first-in, first-out buffer (“FIFO”). A forwarded clock signal was used to clock in data into the FIFO, and a receiver internal clock was used to clock out the data from the FIFO. A delay-locked loop (“DLL”) or phase-locked loop (“PLL”) was used in another conventional circuit to generate a phase-shifted clock signal to account for phase mismatch with the forwarded clock signal and an internal receiver clock signal. In yet another conventional circuit, printed circuit board trace lengths were designed to avoid phase mismatch between the forwarded clock signal and the internal receiver clock signal. However, using a FIFO or a DLL/PLL adds a significant amount of circuitry, and though tailored trace lengths do not necessarily add circuitry, they tend to be inflexible to changes in environment or operation, and tend to be difficult to implement.
More particular with respect to interfacing to a synchronous memory, since the frequencies of the forwarded clock and the receiver clock are the same, it is possible to do a number of computations using data from the source, receiver and the printed circuit board layout to compute a phase difference. The issue with this computation is that it has a large amount of uncertainty due to process, voltage and temperature variations of the source and the receiver. The variation of delays due to the printed circuit board is insignificant by comparison. The uncertainty greatly limits the highest frequency at which one can operate due to the possibility that source and receiver clocks have a window of coincidence. Notably, this uncertainty is not greatly reduced for faster devices. This uncertainty limits interface performance, and it may not be worthwhile to employ faster devices without adding a FIFO.
Accordingly, it would be desirable and useful to provide a source synchronous interface that avoids one or more of the above-mentioned limitations.